TM STM32F4xx Libraries  v1.0.0
Libraries for STM32F4xx devices from Tilen Majerle
tm_stm32f4_mfrc522.h
1 
54 #ifndef TM_MFRC522_H
55 #define TM_MFRC522_H 100
56 
67 #include "stm32f4xx.h"
68 #include "stm32f4xx_rcc.h"
69 #include "stm32f4xx_gpio.h"
70 #include "tm_stm32f4_spi.h"
71 #include "defines.h"
72 
78 /* Default SPI used */
79 #ifndef MFRC522_SPI
80 #define MFRC522_SPI SPI1
81 #define MFRC522_SPI_PINSPACK TM_SPI_PinsPack_2
82 #endif
83 
84 /* Default CS pin used */
85 #ifndef MFRC522_CS_PIN
86 #define MFRC522_CS_RCC RCC_AHB1Periph_GPIOG
87 #define MFRC522_CS_PORT GPIOG
88 #define MFRC522_CS_PIN GPIO_Pin_2
89 #endif
90 
96 typedef enum {
97  MI_OK = 0,
98  MI_NOTAGERR,
99  MI_ERR
100 } TM_MFRC522_Status_t;
101 
102 #define MFRC522_CS_LOW MFRC522_CS_PORT->BSRRH = MFRC522_CS_PIN;
103 #define MFRC522_CS_HIGH MFRC522_CS_PORT->BSRRL = MFRC522_CS_PIN;
104 
105 /* MFRC522 Commands */
106 #define PCD_IDLE 0x00 //NO action; Cancel the current command
107 #define PCD_AUTHENT 0x0E //Authentication Key
108 #define PCD_RECEIVE 0x08 //Receive Data
109 #define PCD_TRANSMIT 0x04 //Transmit data
110 #define PCD_TRANSCEIVE 0x0C //Transmit and receive data,
111 #define PCD_RESETPHASE 0x0F //Reset
112 #define PCD_CALCCRC 0x03 //CRC Calculate
113 
114 /* Mifare_One card command word */
115 #define PICC_REQIDL 0x26 // find the antenna area does not enter hibernation
116 #define PICC_REQALL 0x52 // find all the cards antenna area
117 #define PICC_ANTICOLL 0x93 // anti-collision
118 #define PICC_SElECTTAG 0x93 // election card
119 #define PICC_AUTHENT1A 0x60 // authentication key A
120 #define PICC_AUTHENT1B 0x61 // authentication key B
121 #define PICC_READ 0x30 // Read Block
122 #define PICC_WRITE 0xA0 // write block
123 #define PICC_DECREMENT 0xC0 // debit
124 #define PICC_INCREMENT 0xC1 // recharge
125 #define PICC_RESTORE 0xC2 // transfer block data to the buffer
126 #define PICC_TRANSFER 0xB0 // save the data in the buffer
127 #define PICC_HALT 0x50 // Sleep
128 
129 /* MFRC522 Registers */
130 //Page 0: Command and Status
131 #define MFRC522_REG_RESERVED00 0x00
132 #define MFRC522_REG_COMMAND 0x01
133 #define MFRC522_REG_COMM_IE_N 0x02
134 #define MFRC522_REG_DIV1_EN 0x03
135 #define MFRC522_REG_COMM_IRQ 0x04
136 #define MFRC522_REG_DIV_IRQ 0x05
137 #define MFRC522_REG_ERROR 0x06
138 #define MFRC522_REG_STATUS1 0x07
139 #define MFRC522_REG_STATUS2 0x08
140 #define MFRC522_REG_FIFO_DATA 0x09
141 #define MFRC522_REG_FIFO_LEVEL 0x0A
142 #define MFRC522_REG_WATER_LEVEL 0x0B
143 #define MFRC522_REG_CONTROL 0x0C
144 #define MFRC522_REG_BIT_FRAMING 0x0D
145 #define MFRC522_REG_COLL 0x0E
146 #define MFRC522_REG_RESERVED01 0x0F
147 //Page 1: Command
148 #define MFRC522_REG_RESERVED10 0x10
149 #define MFRC522_REG_MODE 0x11
150 #define MFRC522_REG_TX_MODE 0x12
151 #define MFRC522_REG_RX_MODE 0x13
152 #define MFRC522_REG_TX_CONTROL 0x14
153 #define MFRC522_REG_TX_AUTO 0x15
154 #define MFRC522_REG_TX_SELL 0x16
155 #define MFRC522_REG_RX_SELL 0x17
156 #define MFRC522_REG_RX_THRESHOLD 0x18
157 #define MFRC522_REG_DEMOD 0x19
158 #define MFRC522_REG_RESERVED11 0x1A
159 #define MFRC522_REG_RESERVED12 0x1B
160 #define MFRC522_REG_MIFARE 0x1C
161 #define MFRC522_REG_RESERVED13 0x1D
162 #define MFRC522_REG_RESERVED14 0x1E
163 #define MFRC522_REG_SERIALSPEED 0x1F
164 //Page 2: CFG
165 #define MFRC522_REG_RESERVED20 0x20
166 #define MFRC522_REG_CRC_RESULT_M 0x21
167 #define MFRC522_REG_CRC_RESULT_L 0x22
168 #define MFRC522_REG_RESERVED21 0x23
169 #define MFRC522_REG_MOD_WIDTH 0x24
170 #define MFRC522_REG_RESERVED22 0x25
171 #define MFRC522_REG_RF_CFG 0x26
172 #define MFRC522_REG_GS_N 0x27
173 #define MFRC522_REG_CWGS_PREG 0x28
174 #define MFRC522_REG__MODGS_PREG 0x29
175 #define MFRC522_REG_T_MODE 0x2A
176 #define MFRC522_REG_T_PRESCALER 0x2B
177 #define MFRC522_REG_T_RELOAD_H 0x2C
178 #define MFRC522_REG_T_RELOAD_L 0x2D
179 #define MFRC522_REG_T_COUNTER_VALUE_H 0x2E
180 #define MFRC522_REG_T_COUNTER_VALUE_L 0x2F
181 //Page 3:TestRegister
182 #define MFRC522_REG_RESERVED30 0x30
183 #define MFRC522_REG_TEST_SEL1 0x31
184 #define MFRC522_REG_TEST_SEL2 0x32
185 #define MFRC522_REG_TEST_PIN_EN 0x33
186 #define MFRC522_REG_TEST_PIN_VALUE 0x34
187 #define MFRC522_REG_TEST_BUS 0x35
188 #define MFRC522_REG_AUTO_TEST 0x36
189 #define MFRC522_REG_VERSION 0x37
190 #define MFRC522_REG_ANALOG_TEST 0x38
191 #define MFRC522_REG_TEST_ADC1 0x39
192 #define MFRC522_REG_TEST_ADC2 0x3A
193 #define MFRC522_REG_TEST_ADC0 0x3B
194 #define MFRC522_REG_RESERVED31 0x3C
195 #define MFRC522_REG_RESERVED32 0x3D
196 #define MFRC522_REG_RESERVED33 0x3E
197 #define MFRC522_REG_RESERVED34 0x3F
198 //Dummy byte
199 #define MFRC522_DUMMY 0x00
200 
201 #define MFRC522_MAX_LEN 16
202 
212 extern void TM_MFRC522_Init(void);
213 
224 extern TM_MFRC522_Status_t TM_MFRC522_Check(uint8_t* id);
225 
238 extern TM_MFRC522_Status_t TM_MFRC522_Compare(uint8_t* CardID, uint8_t* CompareID);
239 
243 extern void TM_MFRC522_InitPins(void);
244 extern void TM_MFRC522_WriteRegister(uint8_t addr, uint8_t val);
245 extern uint8_t TM_MFRC522_ReadRegister(uint8_t addr);
246 extern void TM_MFRC522_SetBitMask(uint8_t reg, uint8_t mask);
247 extern void TM_MFRC522_ClearBitMask(uint8_t reg, uint8_t mask);
248 extern void TM_MFRC522_AntennaOn(void);
249 extern void TM_MFRC522_AntennaOff(void);
250 extern void TM_MFRC522_Reset(void);
251 extern TM_MFRC522_Status_t TM_MFRC522_Request(uint8_t reqMode, uint8_t* TagType);
252 extern TM_MFRC522_Status_t TM_MFRC522_ToCard(uint8_t command, uint8_t* sendData, uint8_t sendLen, uint8_t* backData, uint16_t* backLen);
253 extern TM_MFRC522_Status_t TM_MFRC522_Anticoll(uint8_t* serNum);
254 extern void TM_MFRC522_CalculateCRC(uint8_t* pIndata, uint8_t len, uint8_t* pOutData);
255 extern uint8_t TM_MFRC522_SelectTag(uint8_t* serNum);
256 extern TM_MFRC522_Status_t TM_MFRC522_Auth(uint8_t authMode, uint8_t BlockAddr, uint8_t* Sectorkey, uint8_t* serNum);
257 extern TM_MFRC522_Status_t TM_MFRC522_Read(uint8_t blockAddr, uint8_t* recvData);
258 extern TM_MFRC522_Status_t TM_MFRC522_Write(uint8_t blockAddr, uint8_t* writeData);
259 extern void TM_MFRC522_Halt(void);
260 
261 #endif
262